PLANE: A new ATPG system for PLAs

Juinn-Dar Huang, W. Z. Shen

研究成果: Conference contribution

摘要

In this paper, a new PLA ATPG system PLANE is presented. PLANE uses the depth-first sharp operation for efficient test generation. Besides, a powerful test compaction technique using the intersection buffer is applied to get a more compact test set. PLANE also uses parallel fault simulation and backend fault simulation to exploit its performance. Experimental results show that the test length of PLANE is 7.5% shorter than that of PLATYPUS.

原文English
主出版物標題ATS 1993 Proceedings - 2nd Asian Test Symposium
發行者IEEE Computer Society
頁面107-112
頁數6
ISBN(電子)081863930X
DOIs
出版狀態Published - 1 一月 1993
事件2nd IEEE Asian Test Symposium, ATS 1993 - Beijing, China
持續時間: 16 十一月 199318 十一月 1993

出版系列

名字Proceedings of the Asian Test Symposium
ISSN(列印)1081-7735

Conference

Conference2nd IEEE Asian Test Symposium, ATS 1993
國家China
城市Beijing
期間16/11/9318/11/93

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  • 引用此

    Huang, J-D., & Shen, W. Z. (1993). PLANE: A new ATPG system for PLAs. 於 ATS 1993 Proceedings - 2nd Asian Test Symposium (頁 107-112). [398788] (Proceedings of the Asian Test Symposium). IEEE Computer Society. https://doi.org/10.1109/ATS.1993.398788