Performance-preserved analog routing methodology via wire load reduction

Hao Yu Chi, Hwa Yi Tseng, Chien-Nan Liu, Hung-Ming Chen

研究成果: Conference contribution同行評審

6 引文 斯高帕斯(Scopus)

摘要

Analog layout automation is a popular research direction in recent years to raise the design productivity. However, the research on this topic is still not well accepted by analog designers because notable performance loss often exists in tool-generated layout. Most previous works focus on layout placement problem and route the nets implicitly by typical digital routing methodology. This routing approach can solve the net crossing issue easily, but requires a lot of extra vias to connect the horizontal and vertical lines, which significantly increases the wire loads and reduces the circuit performance. In the proposed analog routing flow, we try to route each net with minimum layer changing and consider the wire length simultaneously. In other words, wire load is used as the optimization goal instead of using wire length only to keep the circuit performance after laying out the design. As demonstrated on several cases, this approach significantly reduces the wire load and keeps the similar circuit performance as in manual works.

原文English
主出版物標題ASP-DAC 2018 - 23rd Asia and South Pacific Design Automation Conference, Proceedings
發行者Institute of Electrical and Electronics Engineers Inc.
頁面482-487
頁數6
ISBN(電子)9781509006021
DOIs
出版狀態Published - 20 二月 2018
事件23rd Asia and South Pacific Design Automation Conference, ASP-DAC 2018 - Jeju, Korea, Republic of
持續時間: 22 一月 201825 一月 2018

出版系列

名字Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
2018-January

Conference

Conference23rd Asia and South Pacific Design Automation Conference, ASP-DAC 2018
國家Korea, Republic of
城市Jeju
期間22/01/1825/01/18

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