Performance constraints aware voltage Islands generation in SoC floorplan design

Ming Ching Lu*, Meng Chen Wu, Hung Ming Chen, Hui Ru Jiang

*Corresponding author for this work

研究成果: Conference contribution同行評審

3 引文 斯高帕斯(Scopus)

摘要

Using voltage island methodology to reduce power consumption for System-on-a-Chip (SoC) designs has become more and more popular recently. Currently this approach has been considered either in system-level architecture or post-placement stage. Since hierarchical design and reusable intellectual property (IP) are widely used, it is necessary to optimize floorplanning/ placement methodology considering voltage islands generation to solve power and critical path delay problems. In this paper, we propose a floorplanning methodology considering voltage islands generation and performance constraints. Our method is flexible and can be extended to hierarchical design. The experimental results on some MCNC benchmarks show that our method is effective in meeting performance constraints and simultaneously considers the tradeoff between power routing cost and the assignment of supply voltage in modules.

原文English
主出版物標題2006 IEEE International Systems-on-Chip Conference, SOC
發行者Institute of Electrical and Electronics Engineers Inc.
頁面211-214
頁數4
ISBN(列印)0780397819, 9780780397811
DOIs
出版狀態Published - 1 一月 2006
事件2006 IEEE International Systems-on-Chip Conference, SOC - Austin, TX, United States
持續時間: 24 九月 200627 九月 2006

出版系列

名字2006 IEEE International Systems-on-Chip Conference, SOC

Conference

Conference2006 IEEE International Systems-on-Chip Conference, SOC
國家United States
城市Austin, TX
期間24/09/0627/09/06

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