Performance analysis of data-driven pipelined computer architectures

Kuang Hwei Chi, Chien-Chao Tseng, Chih Zong Lin, Wen Kuang Chou

研究成果: Article同行評審

摘要

This paper presents an analytical model to evaluate the performance of two general approaches, namely fire-matching and match-firing, to designing data-driven pipeline architectures. In both approaches, one or both operands of the dyadic instruction are explicitly stored in memory. Memory locations of the operands are used for matching to determine the enability of the dyadic instruction execution. As the operands are stored in memory explicitly, the organization of memory systems is crucial to the performance of the argument-fetching data-driven pipeline architecture. Therefore, the analytical models are constructed by varying the number of memory banks, sizes of write buffers, and ratio of short-circuiting. The analytical results show that with little support from the memory system, the match-firing approach could outperform the fire-matching approach.

原文English
頁(從 - 到)236-247
頁數12
期刊International Journal of Modelling and Simulation
20
發行號3
DOIs
出版狀態Published - 1 一月 2000

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