Package and Chip Accelerated Aging Methods for Power MOSFET Reliability Evaluation

Tingyou Lin, Chau-Chin Su, Chung-Chih Hung, Karuna Nidhi, Chily Tu, Shao Chang Huang

研究成果: Conference contribution同行評審

1 引文 斯高帕斯(Scopus)

摘要

This paper investigates power MOSFET stress strategies for both package and chip aging evaluation. Two stress test methods are developed to speed up packaging and chip aging process respectively. As a result, the characteristics shifts of package and chip aging can be plotted independently. Thus, the measurement accuracy and measurement time can be improved. A test chip is designed and fabricated in a 0.15μm BCD process. The measured results demonstrate a 10kμm power MOSFET has Ron increased by 72% after 6.3hr stress for the package aging. For the chip aging, the MOSFET has Ron increased by 12% after 600 times stress pulses. The measurement verifies that the accelerated aging in the package and the chip can be controlled separately.

原文English
主出版物標題Proceedings of the 2019 Design, Automation and Test in Europe Conference and Exhibition, DATE 2019
發行者Institute of Electrical and Electronics Engineers Inc.
頁面1661-1666
頁數6
ISBN(電子)9783981926323
DOIs
出版狀態Published - 14 五月 2019
事件22nd Design, Automation and Test in Europe Conference and Exhibition, DATE 2019 - Florence, Italy
持續時間: 25 三月 201929 三月 2019

出版系列

名字Proceedings of the 2019 Design, Automation and Test in Europe Conference and Exhibition, DATE 2019

Conference

Conference22nd Design, Automation and Test in Europe Conference and Exhibition, DATE 2019
國家Italy
城市Florence
期間25/03/1929/03/19

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