Oxide thinning and structure scaling down effect of low-temperature poly-si thin-film transistors

William Cheng Yu Ma*, Tsung Yu Chiang, Je Wei Lin, Tien-Sheng Chao

*Corresponding author for this work

研究成果: Article同行評審

5 引文 斯高帕斯(Scopus)

摘要

In this paper, the gate oxide thickness, and the channel length and width of low-temperature poly-Si thin-film transistors (LTPS-TFTs) have been comprehensively studied. The scaling down of gate oxide thickness from 50 to 20 nm significantly improves the subthreshold swing (S.S.) of LTPS-TFTs from 1.797 V/decade to 0.780 V/decade and the threshold voltage $V TH from 10.87 V to 5.00 V. Moreover, the threshold voltage $V TH roll-off is also improved with the scaling down of gate oxide thickness due to gate capacitance density enhancement. The channel length scaling down also shows significant subthreshold swing S.S. improvement due to a decreasing of the channel grain boundary trap density ${N} t . However, the scaling down of channel length also increases the series resistance effect, resulting in the degradation of the field-effect mobility FE . Therefore, the channel length dependence of field-effect mobility $ FE is slightly different with different channel width due to the competition of channel grain boundary trap density effect and series resistance effect.

原文English
文章編號6030887
頁(從 - 到)12-17
頁數6
期刊IEEE/OSA Journal of Display Technology
8
發行號1
DOIs
出版狀態Published - 1 一月 2012

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