Overview on electrostatic discharge protection designs for mixed-voltage I/O interfaces: Design concept and circuit implementations

Ming-Dou Ker*, Kun Hsien Lin

*Corresponding author for this work

研究成果: Article同行評審

23 引文 斯高帕斯(Scopus)

摘要

Electrostatic discharge (ESD) protection design for mixed-voltage I/O interfaces has been one of the key challenges of system-on-a-chip (SOC) implementation in nano-scale CMOS processes. The on-chip ESD protection circuit for mixed-voltage I/O. interfaces should meet the gate-oxide reliability constraints and prevent the undesired leakage current paths. This paper presents an overview on the design concept and circuit implementations of the ESD protection designs for mixed-voltage I/O interfaces without using the additional thick gate-oxide process. The ESD design constraints in mixed-voltage I/O interfaces, the classification and analysis of ESD protection designs for mixed-voltage I/O interfaces, and the designs of high-voltage-tolerant power-rail ESD clamp circuit are presented and discussed.

原文English
頁(從 - 到)235-246
頁數12
期刊IEEE Transactions on Circuits and Systems I: Regular Papers
53
發行號2
DOIs
出版狀態Published - 1 十二月 2006

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