Optimization on MOS-triggered SCR structures for On-Chip ESD protection

Shih Hung Chen*, Ming-Dou Ker

*Corresponding author for this work

研究成果: Article同行評審

14 引文 斯高帕斯(Scopus)

摘要

MOS-triggered silicon-controlled rectifier (SCR) devices have been reported to achieve efficient on-chip electrostatic discharge (ESD) protection in deep-submicrometer CMOS technology. The channel length of the embedded MOS transistor in the MOS-triggered SCR device dominates the trigger mechanism and current distribution to govern the trigger voltage, holding voltage, on resistance, second breakdown current, and ESD robustness of the MOS-triggered SCR device. The embedded MOS transistor in the MOS-triggered SCR device should be optimized to achieve the most efficient ESD protection in advanced CMOS technology. In addition, the layout style of the embedded MOS transistor can be adjusted to improve the MOS-triggered SCR device for ESD protection.

原文English
頁(從 - 到)1466-1472
頁數7
期刊IEEE Transactions on Electron Devices
56
發行號7
DOIs
出版狀態Published - 5 六月 2009

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