Optimal design of triple-gate devices for high-performance and low-power applications

Meng-Hsueh Chiang, Jeng-Nan Lin, Keunwoo Kim, Ching-Te Chuang

研究成果: Article

6 引文 斯高帕斯(Scopus)

摘要

Pragmatic design of triple-gate (TG) devices is presented by considering corner effects, short-channel effects, and channel-doping profiles. A novel TG MOSFET structure with a polysilicon gate process is proposed using asymmetrical (n(+)/p(+)) polysilicon gates. CMOS-compatible V-T's for high-performance circuit applications can be achieved for both nFET and pFET. The superior subthreshold characteristics and device performance are analyzed and validated by 3-D numerical simulations. Comparisons of device characteristics with a midgap metal gate are presented.
原文English
頁(從 - 到)2423-2428
頁數6
期刊IEEE Transactions on Electron Devices
55
發行號9
DOIs
出版狀態Published - 九月 2008

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