Pragmatic design of triple-gate (TG) devices is presented by considering corner effects, short-channel effects, and channel-doping profiles. A novel TG MOSFET structure with a polysilicon gate process is proposed using asymmetrical (n(+)/p(+)) polysilicon gates. CMOS-compatible V-T's for high-performance circuit applications can be achieved for both nFET and pFET. The superior subthreshold characteristics and device performance are analyzed and validated by 3-D numerical simulations. Comparisons of device characteristics with a midgap metal gate are presented.
Chiang, M-H., Lin, J-N., Kim, K., & Chuang, C-T. (2008). Optimal design of triple-gate devices for high-performance and low-power applications. IEEE Transactions on Electron Devices, 55(9), 2423-2428. https://doi.org/10.1109/TED.2008.927664