On the reduction of reorder buffer size for discrete Fourier transform processor design

Wen Zen Shen*, Yi Hsin Tao, Lan-Rong Dung

*Corresponding author for this work

研究成果: Conference article

3 引文 斯高帕斯(Scopus)

摘要

Double RAM buffer technique is widely used in row-column method to decompose the multidimensional transformation. In this paper, we propose a new approach, named single RAM technique. Base on the accurate arrangement of the location and timing of the input and output data, only a single RAM is used as the reorder buffer. Therefore, approximately half of the memory size is reduced. In addition, a long length DFT processor which can handle 1008-point real-valued DFT with nonstop input sequence is presented to demonstrate the benefits of the single RAM buffer technique. Goertzel Algorithm and CORDIC technique are adopted to realize a two level pipeline linear array for attaining higher speed. Besides, based on the symmetric property of real value DFT, we can compute N-point real-valued DFT with a length-N/2 complex-valued DFT.

原文English
頁(從 - 到)171-174
頁數4
期刊Proceedings - IEEE International Symposium on Circuits and Systems
4
DOIs
出版狀態Published - 1 十二月 1994
事件Proceedings of the 1994 IEEE International Symposium on Circuits and Systems. Part 3 (of 6) - London, England
持續時間: 30 五月 19942 六月 1994

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