On increasing signal integrity with minimal decap insertion in area-array SoC floorplan design

Chao Hung Lu*, Hung-Ming Chen, Chien-Nan Liu

*Corresponding author for this work

研究成果: Conference contribution同行評審

6 引文 斯高帕斯(Scopus)

摘要

With technology further scaling into deep submicron era, power supply noise become an important problem. Power supply noise problem is getting worse due to serious IR-drop and simultaneous switching noise, and decoupling capacitance (decap) insertion is commonly applied to alleviate the noise. There exist some approaches to addressing this issue, but they suffer either from over-design problem or late decap insertion during design stage. In this paper, we propose a methodology to insert decap in a more efficient and effective way during early design stage in area-array designs. The experimental results are encouraging. Compared with other approaches in [15] and [12], we have inserted enough decap to meet supply noise constraint while others employ more area.

原文English
主出版物標題Proceedings of the ASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007
頁面792-797
頁數6
DOIs
出版狀態Published - 1 十二月 2007
事件ASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007 - Yokohama, Japan
持續時間: 23 一月 200727 一月 2007

出版系列

名字Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Conference

ConferenceASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007
國家Japan
城市Yokohama
期間23/01/0727/01/07

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