Aggressive scaling of the gate-oxide thickness has made gate-tunneling current an essential aspect of MOSFET modeling and this leakage current density continues to increase for every process generation. Accurate compact models for gate-tunneling current and its source/drain partition are extremely critical to valid circuit performance in the 90 nm technology or beyond. Gate current partition has been studied by several authors [Cao K, et al. "BSIM4 gate leakage model including source-drain partition," in IEDM Tech. Dig., San Francisco, CA, Dec. 2000. p. 815-8; R. van Langevelde et al., Gate current: modeling, ΔL extraction and impact on RF performance, in IEDM Tech. Dig., Washington, DC, Dec. 2001. p. 289-92; Shih W-K, et al., "A general partition scheme for gate leakage current suitable for MOSFET compact models," in IEDM Tech. Dig., Washington DC., Dec. 2001. p. 293-6]. In this paper, an insight on the common/difference of these different gate leakage current partition schemes into source/drain has been provided and the accuracy of BSIM4 [Cao K, et al. "BSIM4 gate leakage model including source-drain partition," in IEDM Tech. Dig., San Francisco, CA, Dec. 2000. p. 815-8] partition scheme is confirmed with comparing to the new derived equation, which incorporates the gate current into the inhomogeneous term calculation.