On-chip transient voltage suppressor integrated with silicon-based transceiver IC for system-level ESD protection

Che Hao Chuang, Ming-Dou Ker

研究成果: Article同行評審

10 引文 斯高帕斯(Scopus)

摘要

A novel on-chip transient voltage suppressor (TVS) integrated with the silicon-based transceiver IC has been proposed and verified in a 0.8 μm bipolar CMOS DMOS (BCD) process for IEC 61000-4-2 system-level electrostatic discharge (ESD) protection. The structure of on-chip TVS is a high-voltage dual silicon-controlled rectifier (DSCR) with ±16 V of high holding voltage (Vh) under the evaluation of the transmission line pulsing (TLP) system with the pulse width of 100 ns. With the high holding current (Ih) of on-chip TVS, this design can pass ±200 mA latch-up testing. Therefore, the on-chip TVS can be safely applied to protect the RS232 transceiver with the signal level of ±15 V. The RS232 transceiver IC with on-chip TVS has been evaluated to pass the IEC61000-4-2 contact ±12 kV stress without any hardware damages and latch-up issue. Moreover, the proposed RS232 transceiver IC has been verified to well protect the system over the IEC 61000-4-2 contact ±20 kV stress (class B) in the notebook applications.

原文English
文章編號6701176
頁(從 - 到)5615-5621
頁數7
期刊IEEE Transactions on Industrial Electronics
61
發行號10
DOIs
出版狀態Published - 1 一月 2014

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