On-chip ESD protection circuit design with novel substrate-triggered SCR device in sub-quarter-micron CMOS process

Ming-Dou Ker*, Kuo Chun Hsu

*Corresponding author for this work

研究成果: Conference article同行評審

5 引文 斯高帕斯(Scopus)

摘要

A novel design concept to turn on the SCR device by applying the substrate-triggered method is first proposed in the literature for effective on-chip ESD protection design. To avoid the transient-induced latch-up issue, the substrate-triggered SCR devices are stacked in the ESD protection circuits. The turn-on efficiency of SCR can be greatly improved by applying the substrate-triggered method. The on-chip ESD protection circuits designed with the substrate-triggered SCR devices for input pad, output pad, and power pad have been successfully verified in a 0.25-μm CMOS process. The substrate-triggered SCR device with a smaller layout area of only 40μm×20μm can sustain the HBM ESD stress of higher than 7kV.

原文English
期刊Proceedings - IEEE International Symposium on Circuits and Systems
5
DOIs
出版狀態Published - 1 一月 2002
事件2002 IEEE International Symposium on Circuits and Systems - Phoenix, AZ, United States
持續時間: 26 五月 200229 五月 2002

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