Novel method for fabrication of tri-gated poly-Si nanowire field-effect transistors with sublithographic channel dimensions

Ko Hui Lee, Horng-Chih Lin, Tiao Yuan Huang

研究成果: Article同行評審

5 引文 斯高帕斯(Scopus)

摘要

A high-performance short-channel tri-gated polycrystalline-silicon nanowire (NW) field-effect transistor is developed by using simple sidewall spacer and lateral etching techniques without employing costly lithographic tools. Channel length of 120 nm and NW thickness of 25 nm can be easily formed by the self-aligned process. The device exhibits superior electrical characteristics because of the strong gate controllability: a subthreshold swing of 102 mV/dec, drain induced barrier lowing of 74.4 mV/V, and extremely high I ON/IOFF ratio of 4.4 × 108(V d=1 V) are obtained.

原文English
文章編號6515595
頁(從 - 到)720-722
頁數3
期刊IEEE Electron Device Letters
34
發行號6
DOIs
出版狀態Published - 3 六月 2013

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