Novel implantation method to improve machine-model electrostatic discharge robustness of stacked N-channel metal-oxide semiconductors (NMOS) in sub-quarter-micron complementary metal-oxide semiconductors (CMOS) technology

Ming-Dou Ker*, Hsin Chyh Hsu, Jeng Jie Peng

*Corresponding author for this work

研究成果: Article

2 引文 斯高帕斯(Scopus)

摘要

A novel ion implantation method for electrostatic discharge protection, often called as ESD implantation, is proposed to significantly improve machine-model (MM) ESD robustness of N-channel metal-oxide semiconductors (NMOS) device in stacked configuration (stacked NMOS). By using this ESD implantation method, the ESD current is discharged far away from the surface channel of NMOS, therefore the stacked NMOS in the mixed-voltage I/O interface can sustain a much higher ESD level, especially under the MM ESD stress. The MM ESD robustness of the stacked NMOS with a device dimension of W/L = 300 μm/0.5 μm for each NMOS has been successfully improved from the original 358 V to become 491 V in a 0.25-μm complementary metal-oxide semiconductors (CMOS) process.

原文English
頁(從 - 到)L1288-L1290
期刊Japanese Journal of Applied Physics, Part 2: Letters
41
發行號11 B
DOIs
出版狀態Published - 15 十一月 2002

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