Novel ESD implantation for sub-quarter-micron CMOS technology with enhanced machine-model ESD robustness

Ming-Dou Ker, Hsin Chyh Hsu, Jeng Jie Peng

研究成果: Conference contribution同行評審

1 引文 斯高帕斯(Scopus)

摘要

A novel ESD implantation method is proposed to significantly improve machine-model (MM) electrostatic discharge (ESD) robustness of CMOS integrated circuits in sub-quarter-micron CMOS processes. By using this method, the ESD current is discharged far away from the surface channel of NMOS, therefore the NMOS can sustain a much higher ESD level, especially under the machine-model ESD stress. The MM ESD robustness of the gate-grounded NMOS (ggNMOS) with a device dimension of W/L= 300 μm/0.5 μm has been successfully improved from the original 450 V to become 675 V in a 0.25 μm CMOS process.

原文English
主出版物標題Proceedings of the 9th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2002
編輯Wai Kin Chim, John Thong, Wilson Tan, Kheng Chooi Lee
發行者Institute of Electrical and Electronics Engineers Inc.
頁面70-74
頁數5
ISBN(電子)0780374169
DOIs
出版狀態Published - 1 一月 2002
事件9th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2002 - Singapore, Singapore
持續時間: 12 七月 2002 → …

出版系列

名字Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA
2002-January

Conference

Conference9th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2002
國家Singapore
城市Singapore
期間12/07/02 → …

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