Novel design for testability of a mixed-signal VLSIC

E. McShane*, K. Shenai, L. Alkalai, E. Kolawa, V. Boyadzhyan, B. Blaes, Wai-Chi  Fang

*Corresponding author for this work

研究成果: Conference contribution同行評審

2 引文 斯高帕斯(Scopus)

摘要

A novel testability architecture has been developed for a mixed-signal VLSIC which has a functional architecture consisting of a microprocessor core, RF transceiver, and two voltage regulators. It permits a decoupling of analog/RF, digital, and power systems for individual stimulation and analysis. Testing may be performed at the subsystem or block level, and traditional scan techniques are augmented to allow mixed static and dynamic test. This approach aids in identifying any detrimental interaction between individual subsystems by providing isolated between the circuit-under-test and idle circuits.

原文English
主出版物標題Proceedings of the IEEE Great Lakes Symposium on VLSI
發行者IEEE
頁面97-100
頁數4
ISBN(列印)0769501044
DOIs
出版狀態Published - 1 十二月 1999
事件Proceedings of the 1999 9th Great Lakes Symposium on VLSI (GLSVLSI '99) - Ann Arbor, MI, USA
持續時間: 4 三月 19996 三月 1999

出版系列

名字Proceedings of the IEEE Great Lakes Symposium on VLSI
ISSN(列印)1066-1395

Conference

ConferenceProceedings of the 1999 9th Great Lakes Symposium on VLSI (GLSVLSI '99)
城市Ann Arbor, MI, USA
期間4/03/996/03/99

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