Novel CMOS RFIC layout generation with concurrent device placement and fixed-length microstrip routing

Tsun Ming Tseng, Bing Li, Ching Feng Yeh, Hsiang Chieh Jhan, Zuo-Min Tsai , Po-Hung Lin, Ulf Schlichtmann

研究成果: Conference contribution同行評審

1 引文 斯高帕斯(Scopus)

摘要

With advancing process technologies and booming IoT markets, millimeter-wave CMOS RFICs have been widely developed in recent years. Since the performance of CMOS RFICs is very sensitive to the precision of the layout, precise placement of devices and precisely matched microstrip lengths to given values have been a labor-intensive and time-consuming task, and thus become a major bottleneck for time to market. This paper introduces a progressive integer-linear-programming-based method to generate high-quality RFIC layouts satisfying very stringent routing requirements of microstrip lines, including spacing/non-crossing rules, precise length, and bend number minimization, within a given layout area. The resulting RFIC layouts excel in both performance and area with much fewer bends compared with the simulation-tuning based manual layout, while the layout generation time is significantly reduced from weeks to half an hour.

原文English
主出版物標題Proceedings of the 53rd Annual Design Automation Conference, DAC 2016
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(電子)9781450342360
DOIs
出版狀態Published - 5 六月 2016
事件53rd Annual ACM IEEE Design Automation Conference, DAC 2016 - Austin, United States
持續時間: 5 六月 20169 六月 2016

出版系列

名字Proceedings - Design Automation Conference
05-09-June-2016
ISSN(列印)0738-100X

Conference

Conference53rd Annual ACM IEEE Design Automation Conference, DAC 2016
國家United States
城市Austin
期間5/06/169/06/16

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