Non-recursive switch ed-capacitor decimator and interpolator circuits

Chung-Yu Wu, Shou Yuan Huang, Tsai Chung Yu, Yie Yuan Shieu

研究成果: Conference contribution同行評審

3 引文 斯高帕斯(Scopus)

摘要

Non-recursive switched-capacitor decimator and interpolator are developed and analyzed in this paper. Their circuit structures are simple and the design procedure is concise and direct. Moreover, they have the advantages of less clock phases, low sensitivities to component and power-supply variations, good noise performance, and large dynamic range. Two design examples are presented. The consistence of simulation and theoretical results proves the correctness and usefulness of the proposed circuits.

原文English
主出版物標題1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992
發行者Institute of Electrical and Electronics Engineers Inc.
頁面1215-1218
頁數4
ISBN(電子)0780305930
DOIs
出版狀態Published - 1 一月 1992
事件1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992 - San Diego, United States
持續時間: 10 五月 199213 五月 1992

出版系列

名字Proceedings - IEEE International Symposium on Circuits and Systems
3
ISSN(列印)0271-4310

Conference

Conference1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992
國家United States
城市San Diego
期間10/05/9213/05/92

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