Noise-tolerant XOR-based conditional keeper for high fan-in dynamic circuits is presented in this paper. Noise immunity is enhanced by conditionally turning on the conditional keepers. The conditional keeper is turned off at some critical moments to reduce the delay and power consumption. The timing of control signals and their effects on noise immunity, power and delay are also examined. High fanin dynamic circuits are used to demonstrate the effectiveness of the conditional keeper on noise immunity. Distributed power gating combined with clock gating design is also examined. All the simulation results are based on TSMC 100nm CMOS technology. Compared to conventional techniques, under the same unity-gain DC noise criteria, more than 20% power reduction and 20% delay reduction are achieved. Under the same delay criteria, more than 1.25X noise immunity improvement is attained.
|頁（從 - 到）||444-447|
|期刊||Proceedings - IEEE International Symposium on Circuits and Systems|
|出版狀態||Published - 1 十二月 2005|
|事件||IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 - Kobe, Japan|
持續時間: 23 五月 2005 → 26 五月 2005