New true-single-phase-clocking (TSPC) BiCMOS dynamic pipelined logic

Yuh Kuang Tseng*, Chung-Yu Wu

*Corresponding author for this work

研究成果: Conference article同行評審

摘要

New true-single-phase-clocking BiCMOS dynamic logic circuits and BiCMOS dynamic latch logic circuits for high-speed dynamic pipelined system applications are proposed and analyzed. The circuit performance of the new BiCMOS dynamic logic circuits and BiCMOS dynamic latch logic circuits are simulated by using HSPICE in 1μm BiCMOS technology. Simulation results have shown that the operating frequency of the pipelined system which is constructed by the new dynamic latch logic circuits, is 204.1 MHz under 1.5 pF output loading at 2.3 V. It is 2.86 times of the operating frequency in the CMOS TSPC dynamic pipelined system.

原文English
頁(從 - 到)49-52
頁數4
期刊Proceedings - IEEE International Symposium on Circuits and Systems
2
DOIs
出版狀態Published - 1 一月 1998
事件Proceedings of the 1998 IEEE International Symposium on Circuits and Systems, ISCAS. Part 5 (of 6) - Monterey, CA, USA
持續時間: 31 五月 19983 六月 1998

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