New transient detection circuit for system-level ESD protection

Cheng Cheng Yen*, Chi Sheng Liao, Ming-Dou Ker

*Corresponding author for this work

研究成果: Conference contribution同行評審

5 引文 斯高帕斯(Scopus)

摘要

A new on-chip transient detection circuit for system-level electrostatic discharge (ESD) protection is proposed. By including this new proposed on-chip transient detection circuit, a hardware/firmware solution cooperated with power-on reset circuit can be co-designed to fix the system-level ESD issues. The circuit performance to detect different positive and negative ESD-induced fast electrical transients has been investigated by HSPICE simulator and verified in silicon chip. The experimental results in a 0.18-μm CMOS process have confirmed that the proposed on-chip transient detection circuit can detect fast electrical transients during system-level ESD zapping.

原文English
主出版物標題2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT
頁面180-183
頁數4
DOIs
出版狀態Published - 5 九月 2008
事件2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT - Hsinchu, Taiwan
持續時間: 23 四月 200825 四月 2008

出版系列

名字2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT

Conference

Conference2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT
國家Taiwan
城市Hsinchu
期間23/04/0825/04/08

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