New transient detection circuit for on-chip protection design against system-level electrical-transient disturbance

Ming-Dou Ker*, Cheng Cheng Yen

*Corresponding author for this work

研究成果: Article同行評審

14 引文 斯高帕斯(Scopus)

摘要

A new transient detection circuit for on-chip protection design against system-level electrical-transient disturbance is proposed in this paper. The circuit function to detect positive or negative electrical transients under system-level electrostatic-discharge (ESD) and electrical-fast-transient (EFT) testing conditions has been investigated by HSPICE simulation and verified in silicon chip. The experimental results in a 0.18- μm complementary- metaloxidesemiconductor (CMOS) process have confirmed that the new proposed on-chip transient detection circuit can successfully memorize the occurrence of system-level electrical-transient disturbance events. The output of the proposed on-chip transient detection circuit can be used as a firmware index to execute the system recovery procedure. With hardware/firmware codesign, the transient disturbance immunity of microelectronic products equipped with CMOS integrated circuits under system-level ESD or EFT tests can be significantly improved.

原文English
文章編號5406116
頁(從 - 到)3533-3543
頁數11
期刊IEEE Transactions on Industrial Electronics
57
發行號10
DOIs
出版狀態Published - 1 十月 2010

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