摘要
The high leakage or even direct short between contact and gate is a serious problem after the feature sizes are shrunk to 65-nm technology and beyond. However, there is no suitable test structure to effectively monitor the leakage current between them. We have designed a new test structure which can eliminate the drawbacks of existing test structures and effectively monitor the leakage current between contact and gate electrode in state-of-the-art CMOS process technology.
原文 | English |
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文章編號 | 4512068 |
頁(從 - 到) | 244-247 |
頁數 | 4 |
期刊 | IEEE Transactions on Semiconductor Manufacturing |
卷 | 21 |
發行號 | 2 |
DOIs | |
出版狀態 | Published - 1 五月 2008 |