Negative capacitance, n-channel, Si FinFETs: Bi-directional Sub-60 mV/dec, negative DIBL, negative differential resistance and improved short channel effect

Hong Zhou, Daewoong Kwon, Angada B. Sachid, Yuhung Liao, Korok Chatterjee, Ava J. Tan, Ajay K. Yadav, Chen-Ming Hu, Sayeef Salahuddin

研究成果: Conference contribution同行評審

20 引文 斯高帕斯(Scopus)

摘要

We report on negative capacitance (NC) FinFETs with ferroelectric Hf0.5Zr0.5O2 (HZO) as gate dielectric on fully depleted silicon on insulator (FDSOI) substrate with various channel length (LCH) of 450 nm to 30 nm and multiple fin widths (WFIN) of 200 nm to 30 nm. We demonstrate all signature characteristics expected from NCFET: nearly hysteresis free operation (∼3 mV), <60 mV/decade subthreshold swing (SS) with an average SS of 54.5 mV/dec for ∼2 orders of ID and to the best of our knowledge, for the first time in Si MOSFETs, negative Drain Induced Barrier Lowering (DIBL) and Negative Differential Resistance (NDR). Remarkably, we observe significant improvement in the short channel effect compared to control FinFETs: both SS and DIBL are substantially lower for the NCFET for the same Lch/WFin ratio. Importantly, these benefits become increasingly larger for shorter channel lengths.

原文English
主出版物標題2018 IEEE Symposium on VLSI Technology, VLSI Technology 2018
發行者Institute of Electrical and Electronics Engineers Inc.
頁面53-54
頁數2
ISBN(電子)9781538642160
DOIs
出版狀態Published - 25 十月 2018
事件38th IEEE Symposium on VLSI Technology, VLSI Technology 2018 - Honolulu, United States
持續時間: 18 六月 201822 六月 2018

出版系列

名字Digest of Technical Papers - Symposium on VLSI Technology
2018-June
ISSN(列印)0743-1562

Conference

Conference38th IEEE Symposium on VLSI Technology, VLSI Technology 2018
國家United States
城市Honolulu
期間18/06/1822/06/18

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