Multilevel full-chip routing with testability and yield enhancement

Katherine Shu Min Li*, Chung Len Lee, Yao Wen Chang, Chau-Chin Su, Jwu E. Chen

*Corresponding author for this work

研究成果: Paper

2 引文 斯高帕斯(Scopus)

摘要

We propose a multilevel full-chip routing algorithm that improves testability and diagnosability, manufacturability, and signal integrity for yield enhancement. Two major issues are addressed. (1) The oscillation ring (OR) test and its diagnosis scheme for interconnect based on the IEEE P1500 are integrated into the multilevel routing framework to achieve testability enhancement. (2) We present a heuristic to balance routing congestion to optimize the multiple-fault probability, chemical mechanic polishing (CMP) and optical proximity correction (OPC) induced manufacturability, and crosstalk effects, for yield improvement. Experimental results on the MCNC benchmark circuits show that the proposed OR method achieves 100% fault coverage and the maximal diagnosis resolution for interconnects, and the multilevel routing algorithm effectively balances the routing density to achieve 100% routing completion. Compared with [14], the experimental results show that our router improves the maximal congestion by 1.24X - 6.11X in runtime speedup by 1.08X- - 7.66X, and improves the average congestion by 1.00X - 4.52X with the improved congestion deviation by 1.37X - 5.55X.

原文English
頁面29-36
頁數8
DOIs
出版狀態Published - 1 十二月 2005
事件SLIP'05 - 2005 International Workshop on System Level Interconnect Prediction - San Francisco, CA, United States
持續時間: 2 四月 20053 四月 2005

Conference

ConferenceSLIP'05 - 2005 International Workshop on System Level Interconnect Prediction
國家United States
城市San Francisco, CA
期間2/04/053/04/05

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