Multi-core system is becoming the next generation embedded design platform. Heterogeneous and homogeneous processor cores integrated in Multiple Instruction Multiple Data (MIMD) System-on-a-Chip (SoC) to provide complex services, e.g. smart phones, is coming up in the horizon. However, distributed programming is a difficult problem in such systems. Today, only in very few MIMD SoC designs we can find comprehensive multi-core software/hardware co-debug capability that can stop at not only software but also hardware breakpoints to inspect data and system status for identifying bugs. In this work we have integrated various debug mechanisms so that the entire multi-core SoC is able to iterate unlimited times of software and hardware breaks for data and status inspections and stepping forward to resume execution till next break point. This debug mechanism is realized with a chip with four ARM1176 cores and ARM CoreSight™ on-chip debug and trace system, a Field Programmable Gate Array (FPGA) loaded with on-chip test architecture and bus monitor, and software debug platform to download system trace and processor core data for inspection and debug control. Key contributions of this work are (1) a development of multi-clock multi-core software/hardware co-debug platform and (2) the exercise of a multi-core program debugging to visualize the physical behavior of race conditions.