Multi-chip design of analog CMOS expandable modified hamming neural network with on-chip learning and storage for pattern classification

Jeng Feng Lan*, Chung-Yu Wu

*Corresponding author for this work

研究成果: Conference article同行評審

2 引文 斯高帕斯(Scopus)

摘要

In this paper, a multi-chip expandable modified feedforward Hamming neural network for pattern classification is designed and implemented. In the proposed modified Hamming network, the outstar circuit is used to provide the on-chip learning capability. Moreover, the embedded ratio memory in the outstar circuit is used to store the learned pattern. The chips can be connected to form pattern, element, and pattern-and-element-mixed expansions. The experimental results have been correctly verified the operation of multi-chip expansion and classification function. The contrast enhancement characteristic of the stored pattern in the 3-chip element expansion has also been observed.

原文English
頁(從 - 到)565-568
頁數4
期刊Proceedings - IEEE International Symposium on Circuits and Systems
1
DOIs
出版狀態Published - 1 一月 1997
事件Proceedings of the 1997 IEEE International Symposium on Circuits and Systems, ISCAS'97. Part 4 (of 4) - Hong Kong, Hong Kong
持續時間: 9 六月 199712 六月 1997

指紋 深入研究「Multi-chip design of analog CMOS expandable modified hamming neural network with on-chip learning and storage for pattern classification」主題。共同形成了獨特的指紋。

引用此