Monolithic 3D chip integrated with 500ns NVM, 3ps logic circuits and SRAM

Chang Hong Shen, Jia Min Shieh, Tsung Ta Wu, Wen Hsien Huang, Chih Chao Yang, Chih Jen Wan, Chein Din Lin, Hsing Hsiang Wang, Bo Yuan Chen, Guo Wei Huang, Yu Chung Lien, Simon Wong, Chieh Wang, Yin-Chieh Lai, Chien Fu Chen, Meng Fan Chang, Chen-Ming Hu, Fu Liang Yang

研究成果: Conference contribution同行評審

25 引文 斯高帕斯(Scopus)

摘要

For the first time, a sequentially processed sub-50nm monolithic 3D IC with integrated logic/NVM circuits and SRAM is demonstrated using multiple layers of ultrathin-body (UTB) MOSFET-based circuits interconnected through 300nm-thick interlayer dielectric (ILD). High-performance sub-50nm UTB MOSFETs using deposited ultra-flat and ultra-thin (20nm) epi-like Si enable across-layer and in-layer high-speed 3ps logic circuits and 1-T 500ns plasma-MONOS NVMs as well as 6T SRAMs with static noise margin (SNM) of 280 mV and reduced footprint by 25%. Closely stacked monolithic 3D circuits envision advanced high-performance, rich function, and low power intelligent mobile devices.

原文English
主出版物標題2013 IEEE International Electron Devices Meeting, IEDM 2013
DOIs
出版狀態Published - 1 十二月 2013
事件2013 IEEE International Electron Devices Meeting, IEDM 2013 - Washington, DC, United States
持續時間: 9 十二月 201311 十二月 2013

出版系列

名字Technical Digest - International Electron Devices Meeting, IEDM
ISSN(列印)0163-1918

Conference

Conference2013 IEEE International Electron Devices Meeting, IEDM 2013
國家United States
城市Washington, DC
期間9/12/1311/12/13

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