The scaling of CMOSFET's is ultimately limited by the short-channel effects such as Vth roll-off and Drain-Induced-Barrier-Lowering (DIBL). In this paper, a unified physical model is presented for short-channel effects in deep-submicron CMOS transistors taking into account the impacts of channel engineering, defect-enhanced diffusion, and polysilicon gate depletion. The model agrees well with experiment data for several CMOS technologies.
|出版狀態||Published - 1 一月 1997|
|事件||Proceedings of the 1997 International Symposium on VLSI Technology, Systems, and Applications - Taipei, China|
持續時間: 3 六月 1997 → 5 六月 1997
|Conference||Proceedings of the 1997 International Symposium on VLSI Technology, Systems, and Applications|
|期間||3/06/97 → 5/06/97|