Modeling of high voltage LDMOSFET using industry standard BSIM6 MOS model

Chetan Gupta, Harshit Agarwal, Yogesh S. Chauhan, Sourabh Khandelwal, Yen Kai Lin, Chen-Ming Hu, Renaud Gillon

研究成果: Conference contribution同行評審

4 引文 斯高帕斯(Scopus)

摘要

In this paper we have shown the modeling of Lateral Double-Diffused MOS (LDMOS) transistor. A LDMOS structure can be divided into two parts, intrinsic channel and extended drift region. The intinsic channel region is modeled by industry standard BSIM6 model and extended drift region has been modeled by the modified CMC standard model of R3. The R3 model of non-linear resistor, which includes physical effects like velocity-saturation, self-heating etc. has been modified to include gate bias dependency. The new model has been validated with technology computer-aided design (TCAD) simulations and measured data from ON Semiconductor. The model (which is the combination of BSIM6 and R3 models) shows excellent agreement with the TCAD simulations and measured data.

原文English
主出版物標題2016 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2016
發行者Institute of Electrical and Electronics Engineers Inc.
頁面124-127
頁數4
ISBN(電子)9781509018307
DOIs
出版狀態Published - 15 十二月 2016
事件2016 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2016 - Hong Kong, Hong Kong
持續時間: 3 八月 20165 八月 2016

出版系列

名字2016 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2016

Conference

Conference2016 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2016
國家Hong Kong
城市Hong Kong
期間3/08/165/08/16

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