摘要
This paper presents a compact silicon-on-insulator (SOI) model to capture the geometry-dependent floating-body effect using the body-source built-in potential lowering approach. This physically accurate model circumvents the modeling challenge imposed by the trend of the coexistence of partial-depletion (PD) and full-depletion (FD) devices in a single SOI chip by considering short-channel, reverse short-channel and reverse narrow-width floating-body effects. The implication on circuit simulation, under the unified Berkeley short-channel IGFET model-silicon-on-insulator (BSIMSOI) framework, has also been addressed. This geometry-dependent body-source built-in potential lowering model will further enhance the device design of scaled SOI complementary metal-oxide-semiconductor (CMOS) below 100 nm.
原文 | English |
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頁(從 - 到) | 2366-2370 |
頁數 | 5 |
期刊 | Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers |
卷 | 44 |
發行號 | 4 B |
DOIs | |
出版狀態 | Published - 1 四月 2005 |