Microarchitecture-aware floorplanning for processor performance optimization

Chi Ying Chen*, Juinn-Dar Huang, Hung-Ming Chen

*Corresponding author for this work

研究成果: Conference contribution同行評審

摘要

Previous generation floorplanners had objectives focused on smaller area and wirelength. These objectives were considered sufficient since the latencies of interconnects could be neglected. As technology advances and feature size continues to shrink, the communication of signals on interconnects becomes multi-cycled, hence the latencies can not be ignored. These interconnect latencies have impacts on the performance of the processor, and most of state-of-the-art floorplanning frameworks do not consider these issues. In this paper, we propose a methodology based on a heuristic for better performance in terms of microarchitecture and floorplanning, and it is more efficient than previous works shown in the literature. The experimental results from a subset of MIPS show that our methodology can better the processor performance. The perfomance has been improved by up to 35.75% when compared to the floorplanning results from conventional objectives, with few extra overhead on area and wirelength. We also found that the intuition of pressing wirelength for floorplan optimization may not get performance edge.

原文English
主出版物標題2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers
DOIs
出版狀態Published - 28 九月 2007
事件2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Hsinchu, Taiwan
持續時間: 25 四月 200727 四月 2007

出版系列

名字2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers

Conference

Conference2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007
國家Taiwan
城市Hsinchu
期間25/04/0727/04/07

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