Micro-architecture optimization for low-power bitcoin mining ASICs

Yu Zhe Wang, Jingjie Wu, Shi Hao Chen, Mango Chia Tso Chao, Chia Hsiang Yang

研究成果: Conference contribution同行評審

摘要

Cryptocurrencies have recently gained a lot of attention because their high security and easy transaction. Among the current cryptocurrencies, Bitcoin is the most well-known one. Application-specific ICs (ASICs) have been developed in order to deliver high throughput for Bitcoin mining. However, power dissipation is an important issue considering it causes increased mining cost and creates excessive heat. This paper presents three optimization techniques in the micro-architecture level for Bitcoin mining: deep pipelining, speculative computation, and approximate addition. The computations for Bitcoin mining are dominated by SHA-256, which can be realized by two-way 32-stage pipelines. Deep pipelining reduces the critical-path delay, resulting in less power due to architecture transformation and transistor sizing. The iterations of SHA-256 can be early terminated by leveraging speculative computation to prevent unnecessary switches. Approximate addition is adopted to reduce the critical-path delay of the compressor and expander at the cost of negligible precision loss. From the synthesis estimates at a 40-nm technology node, an overall 59.3% power reduction is achieved by applying these three techniques.

原文English
主出版物標題2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(電子)9781728106557
DOIs
出版狀態Published - 四月 2019
事件2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019 - Hsinchu, Taiwan
持續時間: 22 四月 201925 四月 2019

出版系列

名字2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019

Conference

Conference2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019
國家Taiwan
城市Hsinchu
期間22/04/1925/04/19

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