Methodology of generating dual-cell-aware tests

Yu Hao Huang, Ching Ho Lu, Tse Wei Wu, Yu Teng Nien, Ying Yen Chen, Max Wu, Jih Nung Lee, Chia-Tso Chao

研究成果: Conference contribution同行評審

6 引文 斯高帕斯(Scopus)

摘要

This paper introduces a novel fault model, called the dual-cell-Aware (DCA) fault model, which targets the short defects locating between two adjacent standard cells placed in the layout. A layout-based methodology is also presented to automatically extract valid DCA faults from targeted designs and cell libraries. The identified DCA faults are outputted in a format that can be applied to a commercial ATPG tool for test generation. The result of ATPG and fault simulation based on industrial designs have demonstrated that the DCA faults cannot be fully covered by the tests of conventional fault models including stuck-At, transition, bridge and cell-Aware faults and hence require their own designated tests to detect.

原文English
主出版物標題Proceedings - 2017 IEEE 35th VLSI Test Symposium, VTS 2017
發行者IEEE Computer Society
ISBN(電子)9781509044825
DOIs
出版狀態Published - 15 五月 2017
事件35th IEEE VLSI Test Symposium, VTS 2017 - Las Vegas, United States
持續時間: 9 四月 201712 四月 2017

出版系列

名字Proceedings of the IEEE VLSI Test Symposium

Conference

Conference35th IEEE VLSI Test Symposium, VTS 2017
國家United States
城市Las Vegas
期間9/04/1712/04/17

指紋 深入研究「Methodology of generating dual-cell-aware tests」主題。共同形成了獨特的指紋。

引用此