Memory capacity aware non-blocking data transfer on GPGPU

Hao Wei Liu, Hsien Kai Kuo, Kuan Ting Chen, Bo-Cheng Lai

研究成果: Conference contribution

2 引文 斯高帕斯(Scopus)

摘要

The massive data demand of GPGPUs requires expensive memory modules, such as GDDR, to support high data bandwidth. The high cost poses constraints on the total memory capacity available to GPGPUs, and the data need to be transferred between the host CPUs and GPGPUs. However, the long latency of data transfers has resulted in significant performance overhead. To alleviate this issue, the modern GPGPUs have implemented the non-blocking data transfer allowing a GPGPU to perform computing while the data is being transmitted. This paper proposes a capacity aware scheduling algorithm that exploits the non-blocking data transfer in modern GPGPUs. By effectively taking the advantage of non-blocking transfers, experiment results demonstrate an average of 24.01% performance improvement when compared to existing approaches that only consider memory capacity.

原文English
主出版物標題2013 IEEE Workshop on Signal Processing Systems, SiPS 2013
發行者Institute of Electrical and Electronics Engineers Inc.
頁面395-400
頁數6
ISBN(列印)9781467362382
DOIs
出版狀態Published - 1 一月 2013
事件2013 IEEE Workshop on Signal Processing Systems, SiPS 2013 - Taipei, Taiwan
持續時間: 16 十月 201318 十月 2013

出版系列

名字IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation
ISSN(列印)1520-6130

Conference

Conference2013 IEEE Workshop on Signal Processing Systems, SiPS 2013
國家Taiwan
城市Taipei
期間16/10/1318/10/13

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  • 引用此

    Liu, H. W., Kuo, H. K., Chen, K. T., & Lai, B-C. (2013). Memory capacity aware non-blocking data transfer on GPGPU. 於 2013 IEEE Workshop on Signal Processing Systems, SiPS 2013 (頁 395-400). [6674539] (IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/SiPS.2013.6674539