MATERIAL PARAMETERS AFFECTING SURFACE LEAKAGE IN GAAS INTEGRATED CIRCUITS.

Mau-Chung Chang*, C. P. Lee, R. P. Vahrenkamp, L. D. Hou, D. E. Holmes, C. G. Kirkpatrick

*Corresponding author for this work

研究成果: Conference contribution同行評審

2 引文 斯高帕斯(Scopus)

摘要

A pseudo two-dimensional multi-conduction path model has been developed to explain substrate current leakage in GaAs integrated circuits based on trap-fill-limited carrier injection. Injection occurs at the n** plus -p-n** plus region near the substrate surface as a result of the outdiffusion of deep traps. The amount of current leakage and the threshold voltage for sudden current increase are correlated with the EL2 and carbon distribution in the substrate. Good agreement between the experimental results and the theoretical predictions is achieved.

原文English
主出版物標題Unknown Host Publication Title
編輯David C. Look, John S. Blakemore
發行者Shiva Publ Ltd, Nantwich, Engl Also
頁面378-386
頁數9
ISBN(列印)1850140316
出版狀態Published - 1 十二月 1984

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