Low-voltage-triggered PNP devices for ESD protection design in mixed-voltage I/O interface with over-VDD and under-VSS signal levels

Ming-Dou Ker*, Wei Jen Chang, Wen Yu Lo

*Corresponding author for this work

研究成果: Conference contribution同行評審

3 引文 斯高帕斯(Scopus)

摘要

ESD protection design for mixed-voltage I/O interfaces with the low-voltage-triggered PNP (LVTPNP) devices is proposed in this paper. The LVTPNP, by inserting N+ or P+ diffusion across the junction between N-well and P-substrate of the PNP devices, is designed to protect the mixed-voltage I/O pads for signals with voltage levels higher than VDD (over-VDD) and lower than VSS (under-VSS). The experimental results in a 0.35-μm CMOS process have proven that the ESD level of the proposed LVTPNP is higher than that of the traditional PNP device.

原文English
主出版物標題Proceedings - 5th International Symposium on Quality Electronic Design, ISQUED 2004
發行者IEEE Computer Society
頁面433-438
頁數6
ISBN(列印)0769520936, 9780769520933
DOIs
出版狀態Published - 1 一月 2004
事件Proceedings - 5th International Symposium on Quality Electronic Design, ISQED 2004 - San Jose, CA, United States
持續時間: 22 三月 200424 三月 2004

出版系列

名字Proceedings - 5th International Symposium on Quality Electronic Design, ISQUED 2004

Conference

ConferenceProceedings - 5th International Symposium on Quality Electronic Design, ISQED 2004
國家United States
城市San Jose, CA
期間22/03/0424/03/04

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