Low-voltage high-speed programming/erasing floating-gate memory device with gate-all-around polycrystalline silicon nanowire

Ko Hui Lee, Jung Ruey Tsai, Ruey Dar Chang, Horng-Chih Lin, Tiao Yuan Huang

研究成果: Article同行評審

6 引文 斯高帕斯(Scopus)

摘要

A gate-all-around polycrystalline silicon nanowire (NW) floating-gate (FG) memory device was fabricated and characterized in this work. The cross-section of the NW channels was intentionally made to be triangular in shape in order to study the effects of the corners on the device operation. Our results indicate that the channel corners are effective in lowering the programming and erasing (P/E) operation voltages. As compared with the charge-trapping type devices, a larger memory window is obtained with the FG scheme under low-voltage P/E conditions. A model considering the nature of the charge storage medium is proposed to explain the above findings.

原文English
文章編號153102
期刊Applied Physics Letters
103
發行號15
DOIs
出版狀態Published - 7 十月 2013

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