Low temperature polycrystalline silicon thin film transistors fabricated by amorphous silicon spacer structure with pre-patterned TEOS oxide layer

Huang-Chung Cheng*, Chun Chien Tsai, Jian Hao Lu, Ting Kuo Chang, Ching Wei Lin, Bo Ting Chen

*Corresponding author for this work

研究成果: Conference contribution同行評審

摘要

In this paper, location-controlled grain growth with a-Si spacer structure was fabricated. Consequently, High-performance poly-Si TFTs with field-effect mobility exceeding 367 cm 2/V-s and high device uniformity have been fabricated. The excellent electrical characteristics is attributed to large grain and grain boundary elimination in the channel region.

原文English
主出版物標題Proceedings of the International Display Manufacturing Conference and Exhibition, IDMC'05
編輯H.P. David Shieh, F.C. Chen
頁面52-54
頁數3
出版狀態Published - 1 十二月 2005
事件International Display Manufacturing Conference and Exhibition, IDMC'05 - Taipei, Japan
持續時間: 21 二月 200524 二月 2005

出版系列

名字International Display Manufacturing Conference and Exhibition, IDMC'05

Conference

ConferenceInternational Display Manufacturing Conference and Exhibition, IDMC'05
國家Japan
城市Taipei
期間21/02/0524/02/05

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