Low temperature (<180°C) wafer-level and chip-level In-to-Cu and Cu-to-Cu bonding for 3D integration

Yu San Chien*, Yan Pin Huang, Ruoh Ning Tzeng, Ming Shaw Shy, Teu Hua Lin, Kou Hua Chen, Ching Te Chuang, Wei Hwang, Jin-Chern Chiou, Chi Tsung Chiu, Ho Ming Tong, Kuan-Neng Chen

*Corresponding author for this work

研究成果: Conference contribution同行評審

10 引文 斯高帕斯(Scopus)

摘要

Two bonded structures, Cu/In bonding and Cu-Cu bonding with Ti passivation, were investigated for the application of 3D interconnects. For Cu/In bonding, the bonds were achieved at 170°C due to the isothermal solidification. The intermetallic compounds formed in the joint was Cu2In phase. For another case, Cu-Cu bonding with Ti passivation was successfully achieved at 180°C Application of Ti passivation can protect inner Cu from oxidation; therefore, the required bonding temperature can be decreased. Compared to direct Cu-Cu bonding, Cu/In bonding and Cu-Cu bonding with Ti passivation can be performed at low temperature, which can meet low thermal budget requirement for most devices. Besides, with the good electrical performance and reliability, these two bonded interconnects can be applied for 3D IC interconnects.

原文English
主出版物標題2013 IEEE 63rd Electronic Components and Technology Conference, ECTC 2013
發行者IEEE
頁面1146-1152
頁數7
ISBN(列印)9781479902330
DOIs
出版狀態Published - 9 九月 2013
事件2013 IEEE 63rd Electronic Components and Technology Conference, ECTC 2013 - Las Vegas, NV, United States
持續時間: 28 五月 201331 五月 2013

出版系列

名字Proceedings - Electronic Components and Technology Conference
ISSN(列印)0569-5503

Conference

Conference2013 IEEE 63rd Electronic Components and Technology Conference, ECTC 2013
國家United States
城市Las Vegas, NV
期間28/05/1331/05/13

指紋 深入研究「Low temperature (<180°C) wafer-level and chip-level In-to-Cu and Cu-to-Cu bonding for 3D integration」主題。共同形成了獨特的指紋。

引用此