Low power pre-comparison scheme for NOR-Type 10T content addressable memory

Po-Tsang Huang*, Wei Keng Chang, Wei Hwang

*Corresponding author for this work

研究成果: Conference contribution

1 引文 斯高帕斯(Scopus)

摘要

A pre-comparison scheme is designed by using the NOR-type 10T content addressable memory (CAM) between the match line circuits and the pre-charging circuits. Thereby, several bits are pre-compared in advance through the pre-comparison circuit. With the pre-comparison scheme, it will reduce the discharging time and power consumption when the match line is mismatch. The size of the CAM array is about 32 words, and each word has 32bits. The proposed pre-comparison NOR-type 10T CAM can achieve 22.8% power reduction for the 4bits pre-comparison circuit. All the simulation results are based on TSMC 0.13um CMOS technology and the clock frequency is 500MHz.

原文English
主出版物標題APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems
頁面1301-1304
頁數4
DOIs
出版狀態Published - 1 十二月 2006
事件APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems - , Singapore
持續時間: 4 十二月 20066 十二月 2006

出版系列

名字IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS

Conference

ConferenceAPCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems
國家Singapore
期間4/12/066/12/06

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  • 引用此

    Huang, P-T., Chang, W. K., & Hwang, W. (2006). Low power pre-comparison scheme for NOR-Type 10T content addressable memory. 於 APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems (頁 1301-1304). [4145639] (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS). https://doi.org/10.1109/APCCAS.2006.342422