Low-power floating bitline 8-T SRAM design with write assistant circuits

Hao I. Yang*, Ssu Yun Lai, Wei Hwang

*Corresponding author for this work

研究成果: Conference contribution同行評審

3 引文 斯高帕斯(Scopus)

摘要

Low power SRAM plays a key important role on SoC designs. In this paper, low-power floating bitline Read/Write scheme and Write assistant circuits are proposed. Read/Write replica circuits are also designed for wide-voltage range operations. A 32-Kb SRAM subarray is implemented in UMC 90nm CMOS technology. It can operate at 1GHz when Vdd is 1V and at 143MHz when Vdd is 0.5V. Moreover, it consumes around 6.6mW to 670uW during access cycles.

原文English
主出版物標題2008 IEEE International SOC Conference, SOCC
頁面239-242
頁數4
DOIs
出版狀態Published - 1 十二月 2008
事件2008 IEEE International SOC Conference, SOCC - Newport Beach, CA, United States
持續時間: 17 九月 200820 九月 2008

出版系列

名字2008 IEEE International SOC Conference, SOCC

Conference

Conference2008 IEEE International SOC Conference, SOCC
國家United States
城市Newport Beach, CA
期間17/09/0820/09/08

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