Low-leakage tetragonal ZrO 2 (EOT < 1 nm) with in situ plasma interfacial passivation on germanium

Chen Han Chou*, Hao Hsuan Chang, Chung Chun Hsu, Wen Kuan Yeh, Chao Hsin Chien

*Corresponding author for this work

研究成果: Article同行評審

11 引文 斯高帕斯(Scopus)

摘要

We successfully fabricated gate stacks (ZrO 2 /GeO x /Ge) with a subnanometer equivalent oxide thickness (EOT) and low-leakage current on n-/p-Ge through plasma-enhanced atomic layer deposition (ALD). A 0.78-nm-thick GeO x was formed through plasma oxidation (i.e., in situ plasma interfacial passivation, followed by 3.48-nm-thick ZrO 2 growth in the same ALD reactor). A subnanometer EOT of ∼0.9 nm was achieved with a relatively high dielectric constant (roughly 30) of tetragonal-phase ZrO 2 . The gate leakage was ∼ 1 × 10 -4 A/cm 2 at V FB -1V, and roughly 5 × 10 -5 A/cm 2 at V FB +1V on p- and n-type Ge, respectively. Our ZrO 2 stabilized in the tetragonal phase, when the post-deposition annealing temperature, was higher than 500 °C. Therefore, the proposed scheme is simple and effective for use in pursuing an ultralow EOT gate dielectric on Ge.

原文English
文章編號7358074
頁(從 - 到)138-141
頁數4
期刊IEEE Electron Device Letters
37
發行號2
DOIs
出版狀態Published - 1 二月 2016

指紋 深入研究「Low-leakage tetragonal ZrO <sub>2</sub> (EOT < 1 nm) with in situ plasma interfacial passivation on germanium」主題。共同形成了獨特的指紋。

引用此