Low computation cycle and high speed recursive DFT/IDFT: VLSI algorithm and architecture

Lan-Da Van*, Yuan Chu Yu, Chun Ming Huang, Chin Teng Lin

*Corresponding author for this work

研究成果: Conference contribution同行評審

10 引文 斯高帕斯(Scopus)

摘要

In this paper, we propose two low-computation cycle and high-speed recursive discrete Fourier transform (DFT)/inverse DFT (IDFT) architectures adopting the hybrid of Chebyshev polynomial and register-splitting scheme. The proposed core-type recursive architecture achieves half computation-cycle reduction as well as less critical period compared with the conventional second-order DFT/IDFT architecture. So as to further reduce the number of computation cycles, based on the new core-type design, we develop the folded-type recursive DFT/IDFT architecture with the same operating frequency. Moreover, from the derivation results, the operation of DFT and IDFT can be performed with the same structure under different configurations.

原文English
主出版物標題SiPS 2005
主出版物子標題IEEE Workshop on Signal Processing Systems - Design and Implementation, Proceedings
頁面579-584
頁數6
DOIs
出版狀態Published - 1 十二月 2005
事件SiPS 2005: IEEE Workshop on Signal Processing Systems - Design and Implementation - Athens, Greece
持續時間: 2 十一月 20054 十一月 2005

出版系列

名字IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation
2005
ISSN(列印)1520-6130

Conference

ConferenceSiPS 2005: IEEE Workshop on Signal Processing Systems - Design and Implementation
國家Greece
城市Athens
期間2/11/054/11/05

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