Location-controlled-grain Technique for Monolithic 3D BEOL FinFET Circuits

Chih Chao Yang, Tung Ying Hsieh, Po-Tsang Huang, Kuan-Neng Chen, Wan Chi Wu, Shih Wei Chen, Chia He Chang, Chang Hong Shen, Jia Min Shieh, Chen-Ming Hu, Meng Chyi Wu, Wen Kuan Yeh

研究成果: Conference contribution同行評審

3 引文 斯高帕斯(Scopus)

摘要

A location-controlled-grain technique is presented for fabricating BEOL monolithic 3D FinFET ICs over SiO 2 . The grain-boundary free Si FinFETs thus fabricated exhibit steep sub-threshold swing (<70mV/dec.), high driving currents (n-type: 363 μA/μm and p-type: 385 μ Aμm), and high I on /I off (>10 6 ). According to simulation, the thickness of the interlayer dielectric plays an important role and shall be thicker than 250nm so that the sequential pulse laser crystallization process does not heat the bottom devices and interconnects to more than 400 °C.

原文English
主出版物標題2018 IEEE International Electron Devices Meeting, IEDM 2018
發行者Institute of Electrical and Electronics Engineers Inc.
頁面11.3.1-11.3.4
ISBN(電子)9781728119878
DOIs
出版狀態Published - 16 一月 2019
事件64th Annual IEEE International Electron Devices Meeting, IEDM 2018 - San Francisco, United States
持續時間: 1 十二月 20185 十二月 2018

出版系列

名字Technical Digest - International Electron Devices Meeting, IEDM
2018-December
ISSN(列印)0163-1918

Conference

Conference64th Annual IEEE International Electron Devices Meeting, IEDM 2018
國家United States
城市San Francisco
期間1/12/185/12/18

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