Layout styles to improve CDM ESD robustness of integrated circuits in 65-nm CMOS process

Ming-Dou Ker*, Chun Yu Lin, Tang Long Chang

*Corresponding author for this work

研究成果: Conference contribution同行評審

5 引文 斯高帕斯(Scopus)

摘要

Due to the thinner gate oxide in the nanoscale CMOS technology and the larger chip size in the system-on-chip (SoC) IC products, the charged-device-model (CDM) electrostatic discharge (ESD) has become the major ESD events to cause failures during IC manufacturing procedures. The effective ESD protection design against CDM ESD stresses should be implemented into the chip with layout optimization to improve its ESD robustness. In this work, the impacts of different layout styles of MOS devices on CDM ESD robustness were investigated in a 65-nm CMOS process. The experimental results can provide useful information to optimize the layout of integrated circuits against CDM ESD events.

原文English
主出版物標題Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011
頁面374-377
頁數4
DOIs
出版狀態Published - 28 六月 2011
事件2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011 - Hsinchu, Taiwan
持續時間: 25 四月 201128 四月 2011

出版系列

名字Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011

Conference

Conference2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011
國家Taiwan
城市Hsinchu
期間25/04/1128/04/11

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