Layout optimization on ESD diodes for giga-Hz RF and high-speed I/O circuits

Chih Ting Yeh*, Yung Chih Liang, Ming-Dou Ker

*Corresponding author for this work

研究成果: Conference contribution同行評審

1 引文 斯高帕斯(Scopus)

摘要

The diode operated in forward-biased condition has been widely used as an effective on-chip ESD protection device at GHz RF and high-speed I/O pads due to the small parasitic loading effect and high ESD robustness in CMOS integrated circuits (ICs). This work presents new ESD protection diodes realized in the octagon, waffle-hollow, and octagon-hollow layout styles to improve the efficiency of ESD current distribution and to reduce the parasitic capacitance. The new ESD protection diodes can achieve smaller parasitic capacitance under the same ESD robustness level as compared to the waffle diode. Therefore, the signal degradation of GHz RF and high-speed transmission can be reduced due to smaller parasitic capacitance from the new proposed diodes.

原文English
主出版物標題Proceedings of 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010
頁面241-244
頁數4
DOIs
出版狀態Published - 8 十一月 2010
事件2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010 - Hsin Chu, Taiwan
持續時間: 26 四月 201029 四月 2010

出版系列

名字Proceedings of 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010

Conference

Conference2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010
國家Taiwan
城市Hsin Chu
期間26/04/1029/04/10

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