Latehup-like failure of power-rail ESD clamp circuits in CMOS integrated circuits under system-level ESD test

Ming-Dou Ker*, Cheng Cheng Yen

*Corresponding author for this work

研究成果: Conference contribution同行評審

摘要

Two different on-chip power-rail electrostatic discharge (ESD) protection circuits, (1) with NMOS and PMOS feedback; and (2) with cascaded PMOS feedback, have been designed and fabricated in a 0.18-μm CMOS technology to investigate their susceptibility to system-level ESD test. The main purpose for adopting the feedback loop into the power-rail ESD clamp circuits is to avoid the false triggering during a fast power-up operation. However, during the system-level ESD test, where the ICs in a microelectronics system have been powered up, the feedback loop used in the power-rail ESD clamp circuit provides the lock function to keep the main ESD device in a "latch-on" state. The latch-on ESD device, which is often designed with a larger device dimension to sustain high ESD level, conducts a huge current between the power lines to perform a latchup-like failure after the system-level ESD test. The susceptibility of power-rail ESD clamp circuits with the additional board-level noise Alter to the system-level ESD test is also investigated. To meet high system-level ESD specifications, the chip-level ESD protection design should be considered with the transient noise during system-level ESD stress.

原文English
主出版物標題IEEE International Symposium on Electromagnetic Compatibility, EMC 2007
DOIs
出版狀態Published - 1 十二月 2007
事件IEEE International Symposium on Electromagnetic Compatibility, EMC 2007 - Honolulu, HI, United States
持續時間: 9 七月 200713 七月 2007

出版系列

名字IEEE International Symposium on Electromagnetic Compatibility
ISSN(列印)1077-4076

Conference

ConferenceIEEE International Symposium on Electromagnetic Compatibility, EMC 2007
國家United States
城市Honolulu, HI
期間9/07/0713/07/07

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